Introduction to CMOS inverter

• CMOS:

• CMOS stands for Complementary Metal Oxide Semiconductor Field Effect Transistor.

Fig: CMOS circuit

• Advantages of CMOS:

1. High noise margin due to full voltage swing.

2. High input impedance due to IG = 0.

3. Low output impedance, in steady state there always exists a path with finite resistance between output and either VDD or GND, making it less sensitive to noise and disturbances.

4. Ratio less property as the logic of the CMOS does not depend on the W/L ratio of P and N MOSFET.

5. Zero static power dissipation as no direct exists between ground and supply rail under steady state condition.

• The analysis of the gate is done with respect to the different design metrics as listed below:

1. Cost, expressed by the complexity and area.

2.  Integrity and robustness, expressed by the static (or steady-state) behaviour. 

3.  Performance, determined by the dynamic (or transient) response 

4. Energy efficiency, set by the energy and power consumption.

• Logic:

Positive logic = 1:  positive potential

Negative logic = 0: negative potential

When Vin = 1 and equal to VDD the NMOS transistor is ON while the PMOS is OFF.

When Vin = 0 and equal to VSS the PMOS transistor is ON while the NMOS is OFF.

 

• Structure of CMOS logic:

1. Consists of Pull down and Pull up networks.

2. Pull down network has NMOS and Pull up network has PMOS.

3. AND :  NMOS is connected in series; PMOS is connected in parallel.

               OR: NMOS is connected in parallel; PMOS is connected in series.

4. Output is a complement of input.

5. Same inputs are given to both NMOS and PMOS.

6. For N inputs 2N transistors are needed.

7. Pull up transistor is the dual of a pull down transistor.

• Strong 0 and Strong 1 

STRONG 0:

When NMOS and PMOS are given with some voltage let’s say 5V and VDD with 5V and Vt 0.7V the final voltage at the output due to discharging capacity of the capacitor is found to be 0V for NMOS and for PMOS it is 4.3V as we need complete discharge of the voltage we consider NMOS as strong 0.

STRONG 1:

When NMOS and PMOS are given with some voltage let’s say 5V and VDD with 5V and Vt 0.7V the final voltage at the output due to charging capacity of the capacitor is found to be 5V for PMOS and for NMOS it is 0.7V as we need input voltage to be reached as the output voltage so we consider PMOS as strong 1.

Fig: Strong 1 and strong 0 

VTC of CMOS:

Fig : VTC of CMOS

NOTE:

A fast gate is built either by keeping the output capacitance small or by decreasing the on-resistance of the transistor.

• Noise margin:

The amount of noise added to input could hold the output at logic 1 or 0 for the applied input without distortion is called noise margin.

NML = VIL – VOL Low noise margin.

NMH = VOH – VIH High noise margin.

NM =   (NML  + NMH)/2

Fig : Noise margin of CMOS

VIH and VIL are the operational points of the inverter where dvout/dvin = -1 .

• Switching Threshold:

The switching threshold is defined as the point where Vin = Vout. In this region both PMOS and NMOS are always saturated since VDS = VGS.

Let us denote switching threshold as VM (rVDD) /(1 + r)

Switching threshold is set by r which is the comparison of the driving strengths of PMOS and NMOS.

VM is generally located at the middle of the available voltage swing (VDD/2).

Fig 4: Switching Threshold of CMOS

Let’s have analysis based on above graph:

1. VM is relatively insensitive to variations in the device ratio. This means that small variations of the ratio do not disturb the transfer characteristic that much. It is therefore accepted to set the width of the PMOS transistor to values smaller than those required for exact symmetry. 

2. The effect of changing the Wp /Wn ratio is to shift the transient region of the VTC. Increasing the width of the PMOS or the NMOS moves VM towards VDD or GND respectively. This property can be very useful, as asymmetrical transfer characteristics are actually desirable in some designs. 

• Realizing CMOS with Boolean equations:

Fig: 2 input nor gate implementation using CMOS

• CMOS capacitance:

MOSFET capacitances are of three types:

1. Overlap capacitance

2. Channel capacitance

3. Diffusion capacitance

1. Overlap capacitance:

Fig : Overlap capacitance

While fabricating a MOSFET during the etching process there are chances that the gate might overlap with source and drain leading capacitance effect known as overlap capacitance.

COV = COX . Xd. w

Note: COX = £ox/tox

W = width of channel

 Xd = distance between two parallel plates

Channel capacitance:

With varying VGS and VDS and based on region of operation the channel capacitance varies.

1. VGS = 0

There exists no channel so capacitance is seen between metal,  oxide, semiconductor (P/N substrate).

2. VGS > VT; VDS>0

There exists a channel and the dimension of the channel is constant so its linear region of operation and the capacitance is seen between metal, oxide, semiconductor (N/P source and N/P drain).

3. VGS > VT; VDS>>0

In this condition the device is at a saturation region of operation and capacitance is between metal,  oxide, semiconductor (N/P source).

3. Diffusion capacitance:

As the n+ is at drain and source is doped on to the P substrate by diffusion mechanism through the PN junction is reverse biased in MOSFET due to this fabrication we see diffusion capacitance between gate and source and in between gate and drain.

Fig  : Diffusion capacitance

Fig : Internal and external capacitance of CMOS